News
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June 2, 2025
Awarded the inaugural LAD Fellowship to continue working on rapid design of domain-specific hardware accelerators using AI agents for HLS design.
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June 1, 2025
Attended the LLM-Aided Design (LAD) conference in San Francisco, CA, and presented HLS-Eval, the first comprehensive, modular, and reproducible LLM benchmark for HLS design. First conference travel with Lauren!
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March 1, 2025
Successfully passed PhD proposal presentation, planning to defend in 2026 with a major focus on agentic AI for hardware design.
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February 1, 2025
Attended ISFPGA 2025 in Monterey, CA, and hosted a tutorial session with Rishov Sarkar on high-level synthesis (HLS) datasets, benchmarking, and simulation tools.
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September 13, 2023
Attended DAC 2023 in San Francisco, CA, participating in the SIGDA University Demonstration event with a live FPGA demo on the Xilinx ZCU102 board for our INR-Arch work. First time visiting San Francisco!
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February 25, 2023
Attended HPCA 2023 in Montreal, Canada, with colleague Rishov Sarkar, who presented our FlowGNN paper. First time visiting Montreal and Canada!
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January 1, 2023
Started full-time role as Research Faculty at the Georgia Tech Research Institute (GTRI) under the Hardware Security and Trust Division.
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January 1, 2023
Started Ph.D. as a continuation of Master's work under Prof. Callie Hao at Georgia Tech. Business as usual!
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December 16, 2022
Completed Master's degree in Electrical and Computer Engineering at Georgia Tech and walked in the 2022 commencement ceremony! Master's thesis was an initial version of the "GNNBuilder" work under Prof. Callie Hao.
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August 2, 2022
Presented GNNBuilder at the 1st Workshop on Democratizing Domain-Specific Accelerators (WDDSA 2022) as part of MICRO 2022 in Chicago, IL. First time attending MICRO and visiting Chicago!