High-Level Synthesis Synthesis

Early in graduate school, I could never quite figure out how to refer to “synthesis” done as part of the high-level synthesis (HLS) flow.

Normally, one could say “synthesis” when the context is clear — for example, “…after C-simulation and synthesis,” meaning the hardware synthesis step inside an HLS tool. But sometimes I need to be more explicit, and I end up writing something like “…after C-simulation and HLS synthesis.” This appears redundant, but removes any ambiguity, which is good for academic writing and the reader.

Technically, “HLS synthesis” expands to “High-Level Synthesis Synthesis,” which sounds redundant. This is where the “Chai Tea” and “ATM Machine” people come out of the woodworks and say this is bad writing and I need to rewrite my sentences to avoid this silly mistake. Fuck those people; they are annoying.

Now, I believe it is correct and good to say “HLS synthesis”. There are two distinct types of synthesis in hardware design. HLS synthesis (from C/C++ to RTL) is a different process than RTL synthesis (from RTL to gates or a netlist). In fact, in HLS research, talking about both HLS synthesis and RTL synthesis in the same context is common. For example, it is common to compare post-HLS-synthesis estimated results and post-RTL-synthesis results for a design (e.g. while doing design space exploration or training some machine learning models).

One could argue that you can just use “HLS” instead of “HLS synthesis.” However, in the HLS world or within your HLS tool, there are different common “flows” that you can run: C-Simulation (i.e. "csim"), RTL Co-Simulation (i.e. "cosim"), hardware synthesis (“HLS Synthesis”), and hardware export or packaging. It is useful to specifically distinguish the "hardware synthesis" step inside an HLS tool as “HLS synthesis” to refer to the HLS flow that lowers a C++ design all the way to RTL/HDL code via a frontend compiler + scheduling + binding + HDL generation.

There are many more linguistic frontiers yet to be explored in this research area. What is included in the word "implementation"? What is the difference between VLSI vs. EDA? Where is the boundary between new HDL vs. DSL vs. HLS languages? How does an average person interpret the phrases "hardware design" vs. "semiconductor design" vs. "chip design"? Is Tcl pronounced "T-C-L" or "tickle"?

All good questions graduate students should ponder for hours while they wait for their EDA tool to finish running.